Sr. Engineer, Digital Verification

As a Design Verification Engineer, you will play a pivotal role in shaping the future of cutting-edge IoT devices. Immerse yourself in a dynamic environment where you will tackle intricate digital and mixed-signal designs, including sophisticated systems-on-chip (SoCs) featuring multiple CPUs, NPU, ISP, audio sub-system, video processing, digital signal processors, security hardware, and advanced logic architectures.

In this role, you will be able to showcase your expertise in all phases of chip development, from meticulously crafting test plans to constructing robust testbench environments using System Verilog and the Universal Verification Methodology (UVM). Seamlessly integrate third-party VIPs, automate the test environment for efficient boarding, and leverage your in-depth knowledge of SoC architectures, including AMBA AXI/AHB/APB protocols, DMAs, security mechanisms, clock management, and power-gating techniques.

As a key contributor, you will:

· Develop cutting-edge drivers, monitors, predictors, and scoreboards using UVM, ensuring comprehensive verification coverage and functionality validation.

· Craft innovative tests to evaluate power and performance aspects, guaranteeing optimal efficiency and real-world reliability.

· Collaborate with cross-functional teams to perform gate-level simulations and support FPGA and post-silicon bring-up, ensuring a seamless transition from design to deployment.

· Continuously enhance productivity by developing support utilities for verification automation, testbench automation, and regression testing.

· A Bachelor's or Master's  in Electrical Engineering, with 5-10 years of proven experience in block, sub-system, and full-chip verification.

· Disciplined, quality-minded, and highly driven for excellence.

· Expertise in understanding multiple architectures, integrating third-party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges.

· Strong proficiency in System Verilog simulation and C-based verification in an SoC environment.

· Extensive understanding and exposure to design verification for low-power, battery-operated designs.

· Familiarity with ARM processor-based designs and low-power design techniques (preferred).

· Mastery of System Verilog (UVM), Verilog, C/C++, Perl, Python, and Makefile.

· Experience with ARM SoC (preferred), AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, and QoS is required.

· Exposure to AI Edge inference, ISP, Video Codec, Video Processing, Audio Processing, MIPI (CSI/DSI), Crypto, OTP, DSP, and Low-Power technologies (preferred).